Video controllers are used to translate digital video information generated by a computer into a signal for driving a display, such as a monitor or an LCD screen. Video controllers generate images at predetermined resolutions using a predetermined number of colors. Increasingly, users are demanding more colors and higher resolutions. Other considerations being equal, increasing resolution and/or the number of colors negatively impacts the speed at which a video controller can generate an image signal.
The popularity of graphical user interfaces (GUIs), such as Windows and OS/2, has both increased the users' desire for higher resolution, more colors and greater speed. Consequently, many video controllers provide features for increasing the speed at which video data may be processed in a GUI environment. Programs ("drivers") are provided along with the video controller hardware to allow the GUI (or other program) to take advantage of the accelerated features of the video controller.
Each video controller uses a large number of registers to control its operation. Some of these registers are dictated by the video standard being used; for example, the VGA specification dictates a number of registers which must be provided by VGA video controller, such that a program which supports VGA can anticipate the availability of these registers in generating the VGA output. Other registers are specific to enhanced features provided in the particular implementation of the video controller. These registers are accessed only by specific programs to which the manufacturer (or a third party) has written a driver to use the functions provided by these additional registers.
Communicating with a video controller's registers is typically performed through a I/O-mapped read/write cycle. For processors in the INTEL X86 family of microprocessors, an I/O cycle involves setting the M/IO# pin of the processor to a "0" and generating an address on address pins A0-15. Each peripheral which communicates via an I/O-mapped access cycle is assigned a portion of the 64K byte address space provided by the sixteen address bits. The peripherals monitor the M/IO# pin and the address pins to determine whether an I/O cycle is within their address space.
I/O-mapped cycles have certain disadvantages which slow operation of the computer and video controller. Each time an I/O output instruction is issued, the processor's execution is halted until the I/O operation is complete. Thus, the processor waits until completion of the I/O-mapped access, even though the next operation to be performed by the processor may be completely isolated from the I/O operation performed. Further, processors using an execution pipeline (the Intel 80486 has a 4-deep execution buffer) flush the pipeline in a response to an I/O-mapped instruction.
On the other hand, a memory output instruction (i.e., a read/write operation to system memory) can be buffered in the execution pipeline and executed in parallel with subsequent processor instructions. Further, the memory output instructions do not interfere with operating systems such as UNIX and OS/2, in which accessing I/O in a protected mode environment is sometimes not possible.
At least one manufacturer uses memory-mapped register transfers to enhance performance. However, to perform the memory-mapped register accesses, 64K of address space is required just for the memory-mapped registers. This space, in addition to the space for the frame buffer, may significantly reduce the system memory, and requires two address decoders for the registers and frame buffers. Hence, this system is wasteful of both system memory and system address space.
Therefore, a need has arisen in the industry for a video controller having an efficient memory-mapped register addressing method and apparatus.